With $KLAC (-1,3 %) it runs 💪😊

Source

https://ir.kla.com/news-events/press-releases/detail/491/kla-corporation-reports-fiscal-2025-second-quarter-results

Hello everyone,

Yesterday showed me once again how important it is to invest across all sectors. Anyone who invests in individual stocks should "divide" their money into as many different sectors as possible.

Tech stocks did not do so well yesterday, in contrast to some classic blue chips such as $PEP (-2,88 %) or $JNJ (-2,51 %) . Even if these stocks are no longer a huge growth story, they give my portfolio stability in stormy times.

So I was still able to end the day on a positive note yesterday, even though I $AVGO (-0,85 %) and $KLAC (-1,3 %) etc. in my portfolio.

This was probably also due to the low weighting here and there, but I'm still happy about it and feel somehow confirmed that I'm on the right track with my "strategy".

These are my current thoughts on this....how did you see yesterday?

Greetings from DivGrowth1989 ;)

Semiconductor stocks and electricity shares are falling today because of the Deepseek panic. This panic is probably exaggerated. We'll talk about it in tonight's podcast. So be sure to subscribe to the podcast: https://open.spotify.com/show/3SHlvxmpYWkpiWnykajNPa

Semiconductors:

-12% Broadcom $AVGO (-0,85 %)

-12% TSMC $2330
$TSM (-3,3 %)

-11% Nvidia $NVDA (-2,53 %)

-11% BE Semiconductor $SMH (-4,03 %)

-11% ARM Holdings $ARM (-4,35 %)

-11% ASML $ASML (-3,76 %)

-9% Dell $DELL
$DELL (-4,2 %)

-9% Micron $MU (-4,66 %)

-6% AMD $AMD (-7,03 %)

-5% KLA $KLAC (-1,3 %)

Power stocks:

-20% Siemens Energy $ENR (-3,41 %)

-15% Bloom Energy $BE (-1,71 %)

-14% GE Vernova $GEV (+0 %)

-13% Vistra $VST (-1,53 %)

-11% Schneider Electric $SCHNEIDER

#deepseek
#openai
#ai
#ki
#china
#podcast
#spotify
$SPOT (-0,85 %)
#semiconductor
#halbleiter

$TSM (-3,3 %)
$2330

• Revenue: $26.24B (Est. $25.83B) ; +39% YoY
• Net Income: $11.31B (Est. $11.17B) ; +57% YoY
• Gross Margin: 59.0% (Est. 58.5%) ; +53% YoY
• Oper. Margin: 49.0% (Est. 48.1%)
• FY25 CapEx: $38B - $42B (Est. $35.15B)
• FY24 CapEx: $29.76B (Est. ~$29.5B)

Q1'25 Guidance:

• Revenue: $25B - $25.8B (Est. $24.43B)
• Gross Margin: 57% - 59%
• Operating Margin: 46.5% - 48.5% (Est. 46.4%)
• Management expects a ~5.5% sequential revenue drop (smartphone seasonality) but sustained robust AI demand.

Long-Term Revenue CAGR: ~20% (2024-2028)

• AI-related revenue was mid-teens percent of total in 2024 and is expected to double in 2025, with a ~40% CAGR for AI accelerators through 2029.
• AI & HPC cited as main growth engines
• Smartphone & PC segments also gain from higher silicon content

Q4 Process & Segment Details:

• Wafer Shipments: 3.418M; UP +15.6% YoY
• ASP per wafer: ~$6,850 (FY basis); UP +19% YoY
• Advanced Technologies (7nm & below): 74% of total wafer revenue (vs. 69% in Q3)
• 3nm: 26% (vs. 20% in Q3)
• 5nm: 34% (vs. 32% in Q3)
• 7nm: 14% (vs. 17% in Q3)

Q4 revenue by product platform

• HPC (incl. AI): 53% (vs. 51% in Q3) - HPC up +69% YoY
• Smartphone: 35% (vs. 34% in Q3)
• IoT: 5%
• Automotive: 4%
• Consumer Electronics: 1%
• Others: 2%

Q4 Revenue by Geography

• North America: 75% (vs. 71% in Q3)
• China: 9%
• Asia Pacific (ex-China): 9%
• Japan: 4%
• EMEA: 3%

Capital Expenditure:

• FY24 CapEx: $29.76B (Est. ~$29.5B)

- ~70% allocated to advanced nodes (N3, N2)

- ~10-20% for specialty tech & non-wafer (e.g., advanced packaging, mask)

• Sees FY25 CapEx: $38B - $42B (Est. $35.15B)

- "Higher than 2024" to fund advanced nodes (N3, N2) & packaging expansions

- Overseas fabs contribute to increased spending

Advanced Packaging (CoWoS, SoIC):

• ~8% of revenue in 2024; expected to exceed 10% in 2025
• "Any rumors about CoWoS order cuts are simply not true. We continue to increase capacity."

Comment from the management:

Sales drivers and overall performance in the 4th quarter

• "We attribute our sales performance in the fourth quarter to strong demand for 3 nm and 5 nm process technologies."
• "Advanced technologies (7nm and below) accounted for 74% of total wafer sales compared to 69% in the third quarter."

Full year 2024 and future outlook

• "TSMC expects 2025 to be another strong growth year, with revenue growth of over 20% in US dollar terms."
• "Over the next five years (from 2024), we expect a compound annual growth rate (CAGR) of around 20%, driven primarily by AI-related demand and the continued growth of silicon content in smartphones and PCs."

• "In 2024, AI-related revenue was a mid-double-digit percentage of TSMC's total revenue. It is expected to double by 2025 as the strong increase in AI demand continues."

• "We expect a compound annual growth rate (CAGR) of 40% for AI accelerator revenue over the next five years (2025-2029). This is an important driver for future growth."

AI demand, HPC and HBM

• "Memory will grow overall, but HBM (High-Bandwidth Memory) will grow very fast."

• "Demand for AI has more than tripled at TSMC in the last year and we expect it to more than double again in 2025."

• "We continue to see a robust demand profile in AI and can only hope that we can get enough teams and capacity together to support this growth."

Comment on rumors and expansion abroad

• "Rumors about capacity cuts at CoWoS are just rumors - we are continuing to expand our capacity. There are no plans to cut orders."

• "Factories abroad, including in the US and Japan, have an annual gross margin dilution effect of 2-3%, mainly due to smaller scale and higher supply chain costs. We expect this 2-3% margin effect to continue over the next five years."

• "Taiwan will always be the first to ramp up new nodes due to its proximity to our R&D labs (Hsinchu). Other factories abroad will follow depending on customer demand and government support."

• "Our factory in Arizona has started mass production of N4. The second factory is on schedule to produce N3 or N2 technology. Japan's second factory is planned for 2025 and Europe's first factory is also on schedule."

Non-AI markets and silicon content

• "Smartphones are still experiencing low single-digit growth, but the trend towards higher silicon content (AI features, advanced functions) will drive further growth and shorten replacement cycles."

• "PC is similar: overall unit growth is modest, but AI features in PCs are increasing, leading to advanced nodes and higher ASP."

Export controls and demand from China

• "We believe the new US export rules are manageable. We will apply for special licenses for customers as needed, especially in the automotive, industrial or other non-AI use cases."

• "China remains an important market, but currently only accounts for around 9-10% of sales. We continue to work within the regulatory framework."

Silicon photonics and packaging

• "We've had some technical success with silicon photonics, but we probably won't reach significant volumes for another year to a year and a half."

• "Advanced packaging accounted for over 8% of sales in 2024 and is expected to be over 10% in 2025. Our margins for advanced packaging are still slightly below the company average, but are improving."

• "The demand for CoWoS is extremely high for HPC and AI. Other applications (such as smartphones or PCs) may adopt CoWoS in the future, but for now the focus is on AI."

HBM, partnerships and supply chain

• "We are working with all memory manufacturers to provide advanced logic for HBM controllers. It could be another 1.5 years before significant product production from HBM-related logic makes a big revenue contribution."

• "We do not see TSMC as a bottleneck for AI demand. We are expanding capacity for advanced packaging (CoWoS) as quickly as possible and working with memory partners to align capacity."

Margins & pricing strategy

• "We operate in a capital-intensive business and therefore need a healthy gross margin to continue investing in advanced technologies. Pricing must reflect this."

• "We are seeing several cost headwinds including N3 ramps, N2 R&D, conversions from N5 to N3, inflationary pressures and higher costs overseas. We remain confident that we will achieve a gross margin of ~53% or more in the long term."

• "For wafers produced in the US, we are discussing with customers how they will bear the higher costs. Customers understand that the cost structure is different."

Further questions and answers for CEO/CFO

• "We don't comment on competitors' IDMs, we just say that they are important customers. This business is important to us."

• "AI includes CPUs, GPUs, ASICs and HBM logic for HPC/data centers. Edge AI could create 5-10% more chip area in smartphones/PCs, further driving the adoption of advanced nodes."

• "Currently, SoIC is mainly used in AI applications, but we expect more applications in the future."

• "We expect continued strong growth in the AI sector in 2026, although we have not yet made a specific forecast. Our focus is on ensuring sufficient capacity."

• "We are focused on narrowing the cost gap between factories in the US and Japan, but realistically the scale will remain smaller than Taiwan for years to come."

Final note from the CEO

• "2025 will be another strong year. We expect a 20% increase in sales in US dollars, driven by AI and our advanced technologies. We are ramping 3nm and preparing for N2 and beyond to maintain TSMC's technology leadership."

$ASML (-3,76 %) , $ASML (-3,88 %) , $NVDA (-2,53 %) , $AMD (-7,03 %) , $KLAC (-1,3 %) , $QCOM (-5,27 %) , $INTC (-7,5 %) , $MU (-4,66 %) ,

What a turbulent week on the stock market, I had to buy more 😅 How are things looking for you?

$KLAC (-1,3 %)
$ADBE (-0,7 %)
$SIKA (+2,62 %)
$HOLN (+1,18 %)
$MBG (-4,57 %)
$CVX (-2,93 %)
$MRNA (-4,88 %)

From sand to chip: how is a modern semiconductor made?

Reading time: approx. 10min

1) INTRODUCTION

Since 2023 at the latest and the rapid rise of Nvidia $NVDA (-2,53 %) semiconductors and "AI chips" in particular have been the talk of the town. Since then, investors have been chasing after almost every company that has something to do with the manufacture of chips, driving share prices to unimagined heights. However, hardly any investors really know how complex the value chain is within the production of modern chips.

In this article, I will give you an overview of the entire manufacturing process and the companies involved. Even if many of you have a vague idea that the production of modern chips is complex, you will certainly be surprised by how complex it really is in reality.

2) BASIC

The starting point for every chip are so-called wafers [1] - i.e. thin wafers, which usually consist of so-called high-purity monocrystalline silicon. In the field of power semiconductors, which primarily comprises chips for applications with higher currents and voltages, silicon carbide (SiC) or galium nitride (GaN) has recently also been used as the base material for the wafers.

In the so-called front end the actual core components of the chips - the so-called dies - are created and applied to the wafers. The dies are rectangular structures that contain the actual functionality of the later chip. The finished dies are then tested for their functionality and electrical properties. Each die that is found to be good is then integrated into the so-called backend where the individual dies are separated on the wafer. This is followed by the so-called packaging. The individual dies from the front end are then electrically contacted and integrated into a protective housing. In the end, this housing with the contacted die is what is usually called a chip chip.

Now that we have a rough overview of the overall process, let's take a closer look at the individual processes involved in producing the dies on the wafer. This is the area in which most highly complex machines are used and which is usually the most sensitive.

3) FROM SAND TO WAFER

Before wafers made of high-purity silicon can even be produced and the actual process for manufacturing dies can begin, the actual wafer must first be manufactured in almost perfect quality. To do this, quartz sand, which consists largely of silicon dioxide, is reduced with carbon at high temperatures. This produces so-called raw siliconwhich, with a purity of around 96%, is not yet anywhere near the quality required for the production of wafers.

In several chemical processes, which are carried out by Wacker Chemie
$WCH (-3,02 %) or Siltronic
$WAF (-4,36 %) are used to turn the "impure" silicon into so-called polycrystalline silicon with a purity of 99.9999999%. For every billion silicon atoms, there is then only one foreign atom in the silicon. However, this pure polycrystalline silicon is still not suitable for the production of wafers, as the crystal structure in the silicon is not uniform enough. In order to create the right crystal structure, the polycrystalline silicon is then melted again and a so-called ingotwhich is made from monocrystalline silicon is produced. A comparison between raw silicon and the ingot can be found in the following image [3]:

This ingot is then sawn into thin slices, which are then the final wafers for semiconductor production. The best-known wafer producers are Shin Etsu
$4063, (+5,49 %)
Siltronic or GlobalWafers
$6488.

4) FROM THE WAFER TO THE DIE

The wafers described in the previous section can now be used to produce dies. The overall process for producing dies basically consists of applying a large number of layers using various chemical, mechanical and physical processes. The overall process (depending on the product) takes approx. 80 different layers on the wafer, requiring almost 1000 different process steps and 3 months
non-stop production are required [4].

A macroscopic analogy is useful here, which I have also taken from [4]. You can compare the overall process for producing dies with baking a large multi-layer cake. This cake has 80 layers and the recipe for baking consists of 1000 steps. It takes 3 months to make the cake and if even one layer of the cake deviates from the recipe by more than 1%, the whole cake collapses and has to be thrown away.

In the first process steps, the wafer is covered with billions tiny little transistors are created on the wafer, which are then all individually electrically contacted in the following steps. The final steps consist of electrically connecting the transistors to each other, resulting in a complete electrical circuit [4]:

Each individual layer of the approximately 80 layers in the die requires highly specialized processes, which can be roughly summarized as:

• Applying masks: Photolithography, photoresist coating (applying photoresist)
• Apply material: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition
• Remove material: Plasma annealing, Wet annealing, Chemical Mechanical Planarization (CMP)
• Modify material: Ion Implanting, Annealing
• Material cleaning
• Inspecting the layers: Optical, Microscopical, Focused Ion Beam, Defect Inspection

Apply masks

Ultimately, a mask can be thought of as an enlarged copy of the structure of a special layer in the die. These so-called photomasks are then scanned using so-called scanners or steppers "copied" in reduced size onto the wafer. The best-known manufacturer of such lithography systems is ASML
$ASML (-3,76 %). It is currently the only producer of lithography systems that make it possible to produce structures smaller than 10 nanometers on the wafer. In today's powerful and modern chips, such as those found in smartphones, AI chips and processors, the smallest structures are around 3 nanometers in size. Other manufacturers of lithography systems for larger structures (10nm and larger) are Canon Electronics
$7739 or Nikon $7731 (+0,1 %) .

The photomasks - i.e. the enlarged "copies" of the structures - are produced by companies such as Toppan $7911 (+1,8 %) , Dai Nippon Printing
$7912 (+0 %) or Hoya $7741 (-0,67 %) manufactured. Systems for cleaning the photomasks or for applying the photoresist are produced, for example, by Suss Microtec
$SMHN (-6,55 %) for example.

Apply/remove/modify/clean material

As can be seen in the overview above, there are a variety of methods and processes for modifying the material of a particular layer. As a result, there is a lot of different equipment that can handle a process very well with incredible specialization. The best-known and most successful equipment manufacturers include Applied Materials $AMAT (-3,16 %), LAM Research
$LRCX (-3,85 %), Tokyo Electron (TEL)
$8035, (+1,28 %)
Suss Mictrotec, Entegris
$ENTG (-7,79 %) and Axcelis $ACLS (-5,3 %).

The material - for example, highly specialized chemicals - is of course also required for production. Companies such as Linde
$LIN (-3,15 %), Air Liquide
$AI (+0,43 %), Air Products
$APD (-4,49 %) and Nippon Sanso
$4091 (+1,41 %) are major manufacturers of process gases such as nitrogen, hydrogen and argon.

Inspect

As mentioned, every single layer in the manufacturing process of a die must be perfect in order to obtain a functional die at the end. Any small deviation or foreign particles can impair the functionality of the die. As the function of the die can only be checked precisely on the finished die, it is advantageous to inspect the individual layers for defects and deviations during production. Special machines are required for this, which must be able to do different things depending on the layer. Manufacturers of such machines include KLA
$KLAC (-1,3 %) or Onto Innovation
$ONTO (-6,31 %).

The following applies to almost all of the companies mentioned in this section: the companies are highly specialized and have quasi-monopolies on the machines for certain process steps. quasi-monopolies. Suitable equipment therefore usually costs several million dollars. In addition, some of the systems are so complex that they can only be serviced by the manufacturer's own service staff, which results in recurring service revenues for every machine sold. As a rule, each machine requires several highly specialized engineers to ensure long-term stable operation.

5) FROM THE DIE TO THE FINISHED CHIP

Once the wafer has been processed, the dies on the wafer are checked for functionality. There is highly specialized equipment for this, so-called probers. These probers test each individual chip several times, if necessary, to check the functionality implemented in the design. Manufacturers of such probers include Teradyne $TER (-5,91 %), Keysight Technologies
$KEYS (-2,07 %), Onto Innovation or Tokyo Electron. These probers have to control each individual die, some of which are only a few square millimetres in size, and contact the corresponding much smaller test structures with tiny needles. The testing process is sometimes outsourced to entire companies that offer die testing as a complete package. One example of such providers is Amkor Technology
$AMKR (-0,5 %).

The processed and tested wafer is now sawn to obtain individual dies. The dies that are found to be good are then integrated into a protective housing in the backend. The dies that have not passed the functionality test are either sorted out or (depending on the error pattern) processed as a variant with reduced functionality similar to those with full functionality. After a final functional test in the package, the chip is ready for use.

6) FOUNDRIES, FABLESS & SOFTWARE

Now that we have an overview of the complex process of manufacturing a chip, let's zoom out a little further to understand which companies perform which tasks in the semiconductor industry.

It's funny that not once in the manufacturing process has the name Nvidia $NVDA (-2,53 %) or Apple $AAPL (-4,39 %) has been mentioned? Yet they have the most advanced chips, don't they?

The pure production of the chips is done by other companies - so-called foundries. Companies like Nvidia and even AMD $AMD (-7,03 %) are in fact fablessThis means that they do not have their own production facilities but only supply the chip design and let the foundries manufacture the actual chip according to their design.

The design of a chip is like the blueprint for production - the foundries then take over the recipe creation and the actual production. There is special software for designing chips. Companies known for this software include Cadance Design
$CDNS (-2,22 %) and Synopsys $SNPS (+0,17 %). But also the industrial giant Siemens
$SIE (-2,38 %) now also supplies software for designing integrated circuits. Synopsys also offers other software for data analysis within foundry production.

Speaking of foundries; the best known foundry is probably TSMC
$TSM, (-3,3 %) which is the global market leader in foundries. TSMC designs itself no chips itself and specializes exclusively in the production of the most advanced generations of chips. Another major player that also masters the most advanced structure sizes is Samsung $005930. In contrast to TSMC manufactures Samsung also produces its own designs. Other large foundries are Global Foundries
$GFS, (-6,71 %) which was originally a spin-off from AMD and the Taiwanese company United Micro Electronics
$UMC. (-0,89 %)

The best-known fabless companies - i.e. companies without their own chip production - are Nvidia, Apple, AMD, ARM Holdings
$ARM, (-4,35 %)
Broadcom $AVGO (-0,85 %), MediaTek $2454 and Qualcomm $QCOM. (-5,27 %) In the meantime Alphabet $GOOGL, (-2,2 %)
Microsoft $MSFT, (-1,88 %)
Amazon $AMZN (-2,98 %) and Meta $META (-1,91 %) have designed their own chips for certain functionalities and then have them manufactured in foundries.

In addition to foundries and fabless companies, there are of course also hybrid models, i.e. companies that take on both production and design. The best-known examples of this are, of course, companies such as Intel
$INTC (-7,5 %) and Samsung. There is also a whole range of so-called Integrated Device Manufacturer (IDM)which for the most part only manufacture their own designed chips and do not accept customer orders for production. Well-known companies such as Texas Instruments
$TXN, (-5,63 %)
SK Hynix
$000660,
STMicroelectronics
$STMPA, (-6,35 %)
NXP Semiconductors
$NXPI, (-6,51 %)
Infineon $IFX (-5,94 %) and Renesas $6723 (+1,16 %) are among the IDMs.

FINAL WORD

The aim of this article was to provide an overview of the complexity of the semiconductor industry. I do not, of course no claim to be complete, as there are of course many other companies that are part of this value chain. As Getquin thrives on active exchange, I'll give you some food for thought to discuss in the comments below the article:

• feel free to link any other companies in the comments if you think I've forgotten any relevant ones
• what was the most surprising new information for you from the article?
• which companies from the article have you never heard of?
• before reading the article, did you know approximately how a modern chip is produced and what steps are necessary for this?

In general, I can recommend the 20-minute YouTube video at [4] to any interested reader. It provides an excellent animated overview of the manufacturing process of modern chips.

Stay tuned,

Yours Nico Uhlig (aka RealMichaelScott)

SOURCES:

[1] Wikipedia: https://de.wikipedia.org/wiki/Wafer

[2] https://www.halbleiter.org/waferherstellung/einkristall/

[3] https://solarmuseum.org/wp-content/uploads/2019/05/solarmuseum_org-07917.jpg

[4] Branch Education on YouTube: "How are Microchips Made?" https://youtu.be/dX9CGRZwD-w?si=xeV0TYgJ2iwNOKyO

Since the Christmas bonus arrived today, I've also expanded my position a little here 😁👍

Business at KLA continues to be quite solid, latest earnings EPS
7.01$

More info here

Source:

https://ir.kla.com/news-events/press-releases/detail/486/kla-corporation-reports-fiscal-2025-first-quarter-results